Example embodiments generally relate to a semiconductor chip design, and more particularly, to a system and/or method for analyzing timing of a semiconductor chip.
With the miniaturization of semiconductor technology, process variation may increase and chip yield loss may become an important issue.
Statistical static timing analysis (SSTA) may be used to analyze the impact of process variation on the timing of a chip.
According to the SSTA, the timing of a chip is expressed as probability distribution and a probability that the chip satisfies the given timing requirements, e.g., timing yield is estimated from the probability distribution.
SSTA may use the resistance and capacitance information of a semiconductor chip to analyze the wiring disposition and timing of semiconductor logic cells. SSTA is a process of checking whether the semiconductor chip can operate in a given specification, e.g., 100 MHz.
However, when SSTA is used, it may be difficult to accurately estimate the timing yield unless phenomena occurring in chip is accurately reflected.
Therefore, a timing yield analysis method for accurate estimation of timing yield is desired.